This application claims the priority of Korean Patent Application No. 2003-59483, filed on Aug. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an integrated circuit device having an electrostatic discharge (ESD) protection circuit, and more particularly, to an integrated circuit device having an input/output (I/O) ESD protection cell that occupies a small area and performs an ESD protection function.
2. Description of Related Art
In general, ESD protection levels are determined by the composition of an ESD protection circuit, a layout for realizing the ESD protection circuit in an actual integrated circuit device, and a fabricating process used to fabricate the integrated circuit device. While ESD evaluation standards are the same irrespective of the type of integrated circuit device, the size of the integrated circuit device becomes increasingly small and the fabricating process becomes increasingly complicated as the degree of integration of the integrated circuit device becomes higher. Accordingly, it is necessary to develop an ESD protection circuit to effectively perform an ESD protection function in a small area using a fundamental layout design rule determined by a fabricating process.
Currently, most integrated circuit devices include ESD protection circuits for preventing the electrical characteristics of elements from changing or deteriorating due to Human Body Model (HBM) and Machine Model (MM) electrostatic electricity injected into integrated circuit devices when a charged human or metal object touches the integrated circuit devices.
FIG. 1 shows an ESD protection circuit widely used in a conventional integrated circuit device. The integrated circuit device includes a power supply voltage (VDD) line 1 connected to a VDD pad 1a and a ground voltage (VSS) line 2 connected to a VSS pad 2a. An I/O ESD protection cell 3 comprises a VDD ESD protection element 3b and a VSS ESD protection element 3c, which are directly connected to an I/O pad 3a. A power clamp 4 is connected between the VDD pad 1a and the VSS pad 2a to form a path through which an electrostatic current can flow.
Diodes D1 and D2 are widely used as the VDD ESD protection element 3b and the VSS ESD protection element 3c. Since the diodes D1 and D2 have excellent forward characteristics but poor reverse characteristics, the areas of the diodes D1 and D2 should be sufficiently large to be used as ESD protection elements. However, as the integration degree and minuteness degree of an integrated circuit device become increasingly high, the pitch and area of a region for the I/O ESD protection cell 3 are reduced and thus a region for the diodes D1 and D2 is also reduced. Accordingly, it becomes difficult to satisfy ESD protection characteristics in a given area.